The progress of integrated circuit technology has been marked by a continuing reduction in the size of individual devices on each semiconductor chip. Smaller devices yield the dual advantages of greater packing density and increased speed. One of the principal problems currently facing engineers and scientists in the integrated circuit (IC) field is the development of techniques for defining smaller features on the surface of the chip. As is well known, features have conventionally been defined using a photoresist which is exposed, through a mask, to some form of light radiation. Initially, visible light was used, but the desire for smaller feature size has led to the use of UV light and x-rays. However, the minimum feature size that is feasible using optical lithography is approximately 0.2 .mu.m. Currently, development efforts are under way to achieve a transistor which has a gate length of 0.2 .mu.m or less. Thus, a technique is needed for defining features having sizes within this range.